/*
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 * Gary Jennejohn <gj@denx.de>
 * David Mueller <d.mueller@elsoft.ch>
 *
 * Configuation settings for the SAMSUNG SMDK2410 board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
#define CONFIG_S3C2440		1	/* in a SAMSUNG S3C2410 SoC     */
#define CONFIG_MINI2440		1	/* on a SAMSUNG SMDK2410 Board  */

/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ	12000000/* the SMDK2410 has 12MHz input clock */


#define USE_920T_MMU		1
#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */

/*
 * Size of malloc() pool
 */
#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */

/*
 * Hardware drivers
 */
#define CONFIG_DRIVER_DM9000	1	/* we have a DM9000 on-board */
#define CONFIG_DM9000_BASE		0x20000300
#define DM9000_IO     CONFIG_DM9000_BASE
#define DM9000_DATA   (CONFIG_DM9000_BASE+4)
#define CONFIG_DM9000_USE_16BIT         1
#define CONFIG_NET_RETRY_COUNT  10
#define CONFIG_CMD_PING

/*
 * select serial console configuration
 */
#define CONFIG_SERIAL1          1	/* we use SERIAL 1 on SMDK2410 */

/************************************************************
 * RTC
 ************************************************************/
#define	CONFIG_RTC_S3C24X0	1

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_BAUDRATE		115200


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_NAND //added by yellowater


/*#define CONFIG_BOOTDELAY	3*/
/*#define CONFIG_BOOTARGS    	"root=ramfs devfs=mount console=ttySA0,9600" */
#define CONFIG_ETHADDR	08:00:3e:26:0a:5b 
#define CONFIG_NETMASK          255.255.255.0
#define CONFIG_IPADDR		192.168.6.245
#define CONFIG_SERVERIP		192.168.6.78
/*#define CONFIG_BOOTFILE	"elinos-lart" */
/*#define CONFIG_BOOTCOMMAND	"tftp; bootm" */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
#endif

/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP				/* undef to save memory		*/
#define	CFG_PROMPT		"YELLOWATER UBOOT> "	/* Monitor Command Prompt	*/
#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS		16		/* max number of command args	*/
#define 	CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define 	CFG_MEMTEST_START	0x30000000	/* memtest works on	*/
#define 	CFG_MEMTEST_END		0x33F00000	/* 63 MB in DRAM	*/

#undef  	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */

#define	CFG_LOAD_ADDR		0x33000000	/* default load address	*/

/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
/* it to wrap 100 times (total 1562500) to get 1 sec. */
#define	CFG_HZ			1562500

/* valid baudrates */
#define 	CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define 	CONFIG_STACKSIZE	(128*1024)	/* regular stack */
#ifdef 	CONFIG_USE_IRQ
#define 	CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
#define 	CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
#endif

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define 	CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
#define 	PHYS_SDRAM_1		0x30000000 /* SDRAM Bank #1 */
#define 	PHYS_SDRAM_1_SIZE	       0x04000000 /* 64 MB */

#define 	PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */

#define 	CFG_FLASH_BASE		PHYS_FLASH_1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

#define 	CONFIG_AMD_LV800	1	/* uncomment this if you have a LV400 flash */
#if 0
#define 	CONFIG_AMD_LV400	1	/* uncomment this if you have a LV800 flash */
#endif

#define 	CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
#ifdef 	CONFIG_AMD_LV800
#define 	PHYS_FLASH_SIZE		0x00100000 /* 1MB */
#define 	CFG_MAX_FLASH_SECT	(19)	/* max number of sectors on one chip */
#define 	CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
#endif
#ifdef 	CONFIG_AMD_LV400
#define 	PHYS_FLASH_SIZE		0x00080000 /* 512KB */
#define 	CFG_MAX_FLASH_SECT	(11)	/* max number of sectors on one chip */
#define 	CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x070000) /* addr of environment IN NOR FLASH*/
#endif

/* timeout values are in ticks */
#define 	CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* Timeout for Flash Erase */
#define 	CFG_FLASH_WRITE_TOUT	(5*CFG_HZ) /* Timeout for Flash Write */
#define 	CFG_ENV_IS_IN_NAND	 1
#define 	CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector */
#define 	CFG_ENV_OFFSET	0x00030000
#define	CONFIG_BOOTDELAY	5
#define CONFIG_BOOTARGS        "noinitrd root=/dev/mtdblock2 init=/linuxrc console=ttySAC0,115200"
#define CONFIG_BOOTCOMMAND     "nand read 0x30100000 0x50000 0x250000;bootm 0x30100000"
//#define CFG_NAND_LEGACY				/* added by yellowater */





/*-----------------------------------------------------------------------
 * NAND flash settings
 */
#define CONFIG_SYS_NAND_BASE          0      /* NAND控制器基地址*/
#define CONFIG_SYS_MAX_NAND_DEVICE    1      /* 最大nand flash设备数 */
#define NAND_MAX_CHIPS         1       /* nand flash芯片数*/
#define SECTORSIZE             512         /* 1页的大小 */
#define ADDR_COLUMN            1   /* Column地址为1个字节 */
#define ADDR_PAGE              3      /* 页块地址为3个字节 */
#define ADDR_COLUMN_PAGE       4  /* 总地址为4字节 */
#define NAND_ChipID_UNKNOWN    0x00  /* 未知芯片的ID号 */
#define NAND_MAX_FLOORS        1     /* nand 最大层数 */
#define CONFIG_MTD_NAND_VERIFY_WRITE 1  /* 进行写入校验 */

#if defined(CONFIG_CMD_NAND)
#define CFG_NAND_BASE 0x4E000000 
/* NandFlash */
#define CFG_MAX_NAND_DEVICE 	1	
/* Max number of NAND devices		*/

#define NAND_SECTOR_SIZE SECTORSIZE
#define NAND_BLOCK_MASK 511








/* Nand Flash*/
#define WRITE_NAND_ADDRESS(d, adr) {rNFADDR = d;}
#define WRITE_NAND(d, adr) {rNFDATA = d;}
#define READ_NAND(adr) (rNFDATA)
#define NAND_WAIT_READY(nand) {while(!(rNFSTAT&(1<<0)));}
#define WRITE_NAND_COMMAND(d, adr) {rNFCMD = d;}
#define WRITE_NAND_COMMANDW(d, adr)	NF_CmdW(d)

#if defined(CONFIG_S3C2440)
#define NAND_DISABLE_CE(nand) {rNFCONT |= (1<<1);}
#define NAND_ENABLE_CE(nand) {rNFCONT &= ~(1<<1);}
#endif
#if defined(CONFIG_S3C2410)
#define NAND_DISABLE_CE(nand) {rNFCONF |= (1<<11);}
#define NAND_ENABLE_CE(nand) {rNFCONF &= ~(1<<11);}
#endif
/* the following functions are NOP's because S3C24X0 handles this in hardware */

//#define NAND_CTL_CLRALE(nandptr)
//#define NAND_CTL_SETALE(nandptr)
//#define NAND_CTL_CLRCLE(nandptr)
//#define NAND_CTL_SETCLE(nandptr)

/* #undef CONFIG_MTD_NAND_VERIFY_WRITE */
#endif	/* CONFIG_CMD_NAND */

#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_CMDLINE_TAG

#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2   "> "

#define CONFIG_CMDLINE_EDITING

#ifdef CONFIG_CMDLINE_EDITING
#undef CONFIG_AUTO_COMPLETE
#else
#define CONFIG_AUTO_COMPLETE
#endif

/*
* Nandflash Boot
*/
#define STACK_BASE 0x33f00000
#define STACK_SIZE 0x8000
//#define UBOOT_RAM_BASE 0x33f80000
/* NAND Flash Controller */
#define NAND_CTL_BASE 0x4E000000
#define bINT_CTL(Nb)  __REG(INT_CTL_BASE + (Nb))
/* Offset */
#define oNFCONF 0x00

#if defined(CONFIG_S3C2440)
#define CONFIG_S3C2440_NAND_BOOT 1
/* Offset */
#define oNFCONT 0x04
#define oNFCMD 0x08
#define oNFADDR 0x0c
#define oNFDATA 0x10
#define oNFSTAT 0x20
#define oNFECC 0x2c
#define rNFCONF (*(volatile unsigned int *)0x4e000000)
#define rNFCONT (*(volatile unsigned int *)0x4e000004)
#define rNFCMD (*(volatile unsigned char *)0x4e000008)
#define rNFADDR (*(volatile unsigned char *)0x4e00000c)
#define rNFDATA (*(volatile unsigned char *)0x4e000010)
#define rNFSTAT (*(volatile unsigned int *)0x4e000020)
#define rNFECC (*(volatile unsigned int *)0x4e00002c)
#endif

#endif	/* __CONFIG_H */
